We are upgrading the repository! A content freeze is in effect until November 22nd, 2024 - no new submissions will be accepted; however, all content already published will remain publicly available. Please reach out to repository@u.library.arizona.edu with your questions, or if you are a UA affiliate who needs to make content available soon. Note that any new user accounts created after September 22, 2024 will need to be recreated by the user in November after our migration is completed.
Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning
Affiliation
Electrical and Computer Engineering, University of ArizonaIssue Date
2023-02-09Keywords
design space explorationembedded system
high-level synthesis
subspace pruning
System-level optimization
Metadata
Show full item recordCitation
Liao Y, Adegbija T, Lysecky R, Tandon R. (2024). Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. Proceedings of the Great Lakes Symposium on VLSI. 2024. doi:10.1145/3649476.3658738. (170-176). Online publication date: 12-Jun-2024.Rights
© 2023 Copyright held by the owner/author(s). This work is licensed under a Creative Commons Attribution International 4.0 License.Collection Information
This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at repository@u.library.arizona.edu.Abstract
High-level synthesis (HLS) is a rapidly evolving and popular approach to designing, synthesizing, and optimizing embedded systems. Many HLS methodologies utilize design space exploration (DSE) at the post-synthesis stage to find Pareto-optimal hardware implementations for individual components. However, the design space for the system-level Pareto-optimal configurations is orders of magnitude larger than component-level design space, making existing approaches insufficient for system-level DSE. This paper presents Pruned Genetic Design Space Exploration (PG-DSE)-an approach to post-synthesis DSE that involves a pruning method to effectively reduce the system-level design space and an elitist genetic algorithm to accurately find the system-level Pareto-optimal configurations. We evaluate PG-DSE using an autonomous driving application subsystem (ADAS) and three synthetic systems with extremely large design spaces. Experimental results show that PG-DSE can reduce the design space by several orders of magnitude compared to prior work while achieving higher quality results (an average improvement of 58.1x). © 2023 Copyright held by the owner/author(s).Note
Open access articleVersion
Final Published VersionScopus Count
Collections
Except where otherwise noted, this item's license is described as © 2023 Copyright held by the owner/author(s). This work is licensed under a Creative Commons Attribution International 4.0 License.